Alif Semiconductor /AE302F40C1537LE_CM55_HE_View /GPU2D /GPU2D_CONTROL

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Interpret as GPU2D_CONTROL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0D2C_LIMNENABLE 0D2C_QUADNENABLE 0D2C_LIMNTHRESHOLD 0D2C_BAND1ENABLE 0 (D2C_UNION12)D2C_UNION12 0 (D2C_UNION34)D2C_UNION34 0 (D2C_UNION56)D2C_UNION56 0 (D2C_UNIONAB)D2C_UNIONAB 0 (D2C_UNIONCD)D2C_UNIONCD 0 (D2C_SPANABORT)D2C_SPANABORT 0 (D2C_SPANSTORE)D2C_SPANSTORE 0 (D2C_LIMITERPRECISION)D2C_LIMITERPRECISION

Description

Geometry Control Register

Fields

D2C_LIMNENABLE

Limiter N enable Bit 5: Limiter 6 enable Bit 4: Limiter 5 enable Bit 3: Limiter 4 enable Bit 2: Limiter 3 enable Bit 1: Limiter 2 enable Bit 0: Limiter 1 enable

D2C_QUADNENABLE

Quadratic coupling N enable Bit 8: Quadratic coupling 3 enable Bit 7: Quadratic coupling 2 enable Bit 6: Quadratic coupling 1 enable

D2C_LIMNTHRESHOLD

Limiter N threshold enable Bit 14: Limiter 6 threshold enable Bit 13: Limiter 5 threshold enable Bit 12: Limiter 4 threshold enable Bit 11: Limiter 3 threshold enable Bit 10: Limiter 2 threshold enable Bit 9: Limiter 1 threshold enable

D2C_BAND1ENABLE

Band filter N enable Bit 16: Band filter 2 enable Bit 15: Band filter 1 enable

D2C_UNION12

Combine 1/2 as union (+) otherwise intersect (*)

D2C_UNION34

Combine 3/4 as union (+) otherwise intersect (*)

D2C_UNION56

Combine 5/6 as union (+) otherwise intersect (*)

D2C_UNIONAB

Combine (12)/(34) as union

D2C_UNIONCD

Combine (AB)/(56) as union

D2C_SPANABORT

Enable span abort

D2C_SPANSTORE

Enable span store

D2C_LIMITERPRECISION

Limiter precision is increased by 6 (10.22)

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